Everspin xSPI STT-MRAM code and data integration application scenario

  In this use case scenario, the application code and some small amount of data are stored within the same memory chip. This is sometimes required to meet stringent cost and space (as in physical board space) requirements. The code is loaded in RAM at boot time. A file system can be used for storing the data and possibly the firmware, but oftentimes raw accesses are used. Because of its low cost and small footprint, NOR flash is com‐monly used for this purpose.
 
  For read‐only or read‐centric workloads, this de‐sign works just fine. However, due to poor write performances and high write energy consumption,NOR flash is generally ill‐suited even for mod‐erate write workloads. NAND flash could also be used to improve write performances, but it comes with an additional level of complexity due to bad block and soft error management. Another issue is endurance. Although most applications will never get near the maximum 100K erase cy‐cles of NOR or SLC NAND, retention decreases significantly with cell wear. From the typical 10‐year specification for an unworn device, the re‐tention might drop to only 1 year after 10K cy‐cles. If the firmware image ever ends up in worn blocks (which may happen given that proper wear‐levelling is used) this can become a problem.
 
  With capacities up to 64 Mb packed inside a com‐pact 8 DFN, the EMxxLX familly is a perfect fit for this particular use case. It has an extremely high write speed, low write energy consumption and virtually unlimited write endurance. As of now, NOR flash still has a capacity advantage over MRAM, but large NOR chips are not exactly cheap and there is no sign that MRAM cannot scale up to that combined level of size and cost. In fact,Everspin is already working on additional MRAM products with densities higher than 64Mb.